(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to field effect transistors having sub-quarter micrometer channel lengths and lightly doped drains (LDD).
(2) Description of the Prior Art
Recent advances in the semiconductor process technologies in the past few years have dramatically decreased the device feature size and increased the circuit density and performance on integrated circuit chips. The device most used for Ultra Large Scale Integration (ULSI) is the Field Effect Transistor (FET), having a silicon gate electrode and self-aligned source/drain contact areas. The popular choice of FETs is because of their very small size, high packing density, low power consumption and high yields.
The conventional FETs are typically fabricated by patterning polysilicon gate electrodes over a thin gate oxide on a single crystal semiconductor substrate. The gate electrode structure is used as a diffusion or implant barrier mask to form self-aligned source/drain areas in the substrate adjacent to the sides of the gate electrode. The distance from the source junction to drain junction under the gate electrode is defined as the channel length of the FET.
Advances in semiconductor technologies, such as high resolution photolithographic techniques and anisotropic plasma etching, to name a few have reduced the minimum feature sizes on devices to less than a micrometer. For example, FETs are currently used in the industry having channel lengths that are less than a half micrometer (0.5 um) in length. If further increases in circuit density and device performance are to continue, then device minimum feature sizes and more specifically, the FET channel length must be reduced to sub-quarter micrometer dimensions (that is to less than 0.25 um).
However, as this down scaling continues and the channel length is further reduced in length, the FET device experiences a number of undesirable electrical characteristics known as short channel effects (SCE). These short channel effects become more severe as the device physical dimensions are scaled down. This result is due to the fact that the band gap and built in potential at junctions are a constant of crystalline material and non-scalable.
These adverse short channel effects result from the electric field distribution in the channel area when the integrated circuit is powered up, which lead to a number of problems. For example, electrons ejected from the drain can acquire sufficient energy to be injected into the gate oxide resulting in charge build up in the oxide that causes threshold voltage shifts. Unfortunately, this hot electron effect can degrade device performance after the product is in use (at the customer). Another adverse effect is the threshold voltage lowering referred to as threshold voltage roll-off. The decrease in threshold voltage (V.sub.th) with reduced channel length occurs when the channel length is comparable to the source/drain junction depth.
To minimize the short channel effects, it is common practice in the semiconductor industry to fabricate FET structures with double diffused drains (DDD) or Lightly Doped Drains (LDD). These DDD of LDD FET structures, having low dopant concentration in the drains adjacent to the gate electrodes, modify the electric fields in the drain so as to minimize or eliminate the hot electron and roll-off effects. The short channel effect of threshold voltage roll-off can also be minimized by forming drains with shallow junction depths.
Another problem occurring with the conventional FETs, having patterned gate electrodes, is the limitations of the current photolithographic techniques to repeatedly and reliably produce sub-quarter micrometer (&lt;0.25 um) wide gate electrode structures.
The reverse self-aligned field effect transistor process as been suggested as an alternative to conventional FETs for forming sub-micrometer gate electrode structures. For example, a method of forming one of these alternate FET structure is described by W. J. Boardman, et al U.S. Pat. No. 5,196,357. However, in this patent the thin gate oxide between the source/drain sidewalls and the gate electrode can result in a high gate to source/drain capacitance and reduced device performance. Other examples for making reverse self-aligned FETs is described by N. Tsai, U.S. Pat. No. 5,071780, and by H. Arima et al, U.S. Pat. No. 5,141,891. A related structure having a grooved channel region in the FET is described in a paper entitled "A Sub-0.1-um Grooved Gate MOSFET with High Immunity to Short-Channel Effects", by J. Tanaka et al, in the IEDM Proceedings of the IEEE, 1993 pages 537-540.
In these reverse self-aligned FET structures a multilayer usually having a polysilicon layer, as one of the layers is deposited over the device areas where the FETs are to be built. Openings having vertical sidewalls are etched in the multilayer at locations where the FET gate electrodes are to be formed. A gate oxide and sidewall insulating layers are formed in the opening and a second conducting layer is then deposited and patterned to form the self-aligned overlapping gate electrode. The patterned multilayer and out diffusion of dopant impurities therefrom an into the substrate serves as the source/drain areas of the FET. However, a number of problems still occur that make manufacturing these FETs difficult, such as etch control during patterning of layers and the ability to fabricate shallow source/drain junctions.
Therefore, there is still a strong need in the semiconductor industry for a more controllable and cost effective manufacturing process for forming reverse self-aligned field effect transistors having shallow lightly doped drains that are immunity from short channel effects.